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Integrated Circuit Systems, Inc.
ICS8547
HEX, LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS CLOCK BUFFERS
FEATURES
* 12 LVDS outputs * Selectable CLKx, nCLKx inputs * CLKx, nCLKx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL * Maximum output frequency: 700MHz * Translates any differential input signal (LVPECL, LVHSTL, SSTL, DCM) to LVDS levels without external bias networks * Translates any single-ended input signal to LVDS with resistor bias on nCLKx input * Output skew: 250ps (maximum) * Bank skew: 15ps (maximum) * Part-to-part skew: 500ps (maximum) * Propagation delay: 1.8ns (maximum) * 3.3V operating supply * 0C to 85C ambient operating temperature * Industrial temperature information available upon request
GENERAL DESCRIPTION
The ICS8547 is a Hex low skew, high performance 1-to-2 Differential-to-LVDS Clock Buffer HiPerClockSTM and a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. Utilizing Low Voltage Differential Signaling (LVDS) the ICS8547 provides a low power, low noise, point-to-point solution for distributing clock signals over controlled impedances of 100. The ICS8547 has six selectable clock inputs. The CLKx, nCLKx pairs can accept any differential input levels and translates them to 3.3V LVDS output levels.
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Guaranteed output and part-to-part skew specifications make the ICS8547 ideal for those applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
CLK0 nCLK0 Q0A nQ0A Q0B nQ0B
Q1A nQ1A Q1B nQ1B
PIN ASSIGNMENT
VDDO GND VDD Q3B nQ3B nQ3A Q3A nCLK3 CLK3 VDD GND VDDO
48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24
CLK1 nCLK1
CLK2 nCLK2
Q2A nQ2A Q2B nQ2B
Q3A nQ3A Q3B nQ3B
CLK3 nCLK3
Q4A nQ4A nQ4B Q4B nCLK4 CLK4 CLK5 nCLK5 Q5B nQ5B nQ5A Q5A
ICS8547
Q2A nQ2A nQ2B Q2B nCLK2 CLK2 CLK1 nCLK1 Q1B nQ1B nQ1A Q1A
VDDO GND VDD Q0B nQ0B nQ0A Q0A nCLK0 CLK0 VDD GND VDDO
CLK4 nCLK4
Q4A nQ4A Q4B nQ4B
CLK5 nCLK5
Q5A nQ5A Q5B nQ5B
48-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View
ICS8547AY
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REV. A FEBRUARY 4, 2003
Integrated Circuit Systems, Inc.
ICS8547
HEX, LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS CLOCK BUFFERS
Type Output Output Input Input Input Input Output Output Power Power Power Input Input Output Output Output Output Input Input Input Input Output Output Output Output Input Input Pullup Pulldown Pullup Pulldown Pulldown Pullup Pulldown Pullup Pullup Pulldown Pulldown Pullup Description Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Inver ting differential clock input. Non-inver ting differential clock input. Non-inver ting differential clock input. Inver ting differential clock input. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Output supply pins. Power supply ground. Core supply pins. Non-inver ting differential clock input. Inver ting differential clock input. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Inver ting differential clock input. Non-inver ting differential clock input. Non-inver ting differential clock input. Inver ting differential clock input. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Inver ting differential clock input. Non-inver ting differential clock input.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 4 5 6 7 8 9, 10 11, 12 13, 24, 37, 48 14, 23, 38, 47 15, 22, 39, 46 16 17 18, 19 20, 21 25, 26 27, 28 29 30 31 32 33, 34 35, 36 40, 41 42, 43 44 45 Name Q4A, nQ4A nQ4B, Q4B nCLK4 CLK4 CLK5 nCLK5 Q5B, nQ5B nQ5A, Q5A VDDO GND VDD CLK0 nCLK0 Q0A, nQ0A nQ0B, Q0B Q1A, nQ1A nQ1B, Q1B nCLK1 CLK1 CLK2 nCLK2 Q2B, nQ2B nQ2A, Q2A Q3B, nQ3B nQ3A, Q3A nCLK3 CLK3
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
ICS8547AY
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REV. A FEBRUARY 4, 2003
Integrated Circuit Systems, Inc.
ICS8547
HEX, LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS CLOCK BUFFERS
Test Conditions Minimum Typical 51 51 1 Maximum 4 Units pF K K pF
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN CPD Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Capacitance Power Dissipation
TABLE 3. CLOCK INPUT FUNCTION TABLE
Inputs CLKx 0 1 0 1 Biased; NOTE 1 Biased; NOTE 1 nCLKx 1 0 Biased; NOTE 1 Biased; NOTE 1 0 1 Q0A:Q5A, Q0B:Q5B LOW HIGH LOW HIGH HIGH LOW Outputs nQ0A:nQ5A, nQ5B:nQ5B HIGH LOW HIGH LOW LOW HIGH Input to Output Mode Differential to Differential Differential to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting Inver ting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
ICS8547AY
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REV. A FEBRUARY 4, 2003
Integrated Circuit Systems, Inc.
ICS8547
HEX, LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS CLOCK BUFFERS
4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V 47.9C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0C TO 85C
Symbol VDD VDDO IDD IDDO Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 Maximum 3.465 3.465 22 18 Units V V mA mA
TABLE 4B. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0C TO 85C
Symbol IIH IIL VPP VCMR Parameter Input High Current CLKx nCLKx Input Low Current CLKx nCLKx Test Conditions VIN = VDD = 3.465V VIN = VDD = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 0.15 0.5 1.3 VDD - 0.85 Minimum Typical Maximum 150 5 Units A A A A V V
Peak-to-Peak Voltage Common Mode Voltage Range
TABLE 4C. LVDS DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0C TO 85C
Symbol VOD VOD VOS VOS IOFF IOSD IOS/IOSB Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change Power Off Leakage Differential Output Shor t Circuit Current Output Shor t Circuit Current -1 1.0 1.3 Test Conditions Minimum 175 Typical 275 Maximum 375 50 1.6 50 +1 -5.5 -12 Units mV mV V mV A mA mA
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REV. A FEBRUARY 4, 2003
Integrated Circuit Systems, Inc.
ICS8547
HEX, LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS CLOCK BUFFERS
Test Conditions 500MHz Minimum 1.2 Typical 1.5 Maximum 700 1.8 250 15 500 20% to 80% 300MHz 250 45 50 550 55 60 Units MHz ns ps ps ps ps % %
TABLE 5. AC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0C TO 85C
Symbol fMAX tPD Parameter Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 5 Bank Skew; NOTE 3, 5 Par t-to-Par t Skew; NOTE 4, 5 Output Rise/Fall Time Output Duty Cycle
tsk(o) tsk(b) tsk(pp)
tR / tF odc
300MHz < 500MHz 40 All parameters measured at 500MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured from at the output differential cross points. NOTE 3: Defined as skew within a bank of outputs at the same voltages and with equal load conditions. NOTE 4: Defined as between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
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REV. A FEBRUARY 4, 2003
Integrated Circuit Systems, Inc.
ICS8547
HEX, LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS CLOCK BUFFERS
PARAMETER MEASUREMENT INFORMATION
VDD 3.3V nCLKx
Qx
3.3V5% POWER SUPPLY + Float GND -
SCOPE
V
CLKx
PP
Cross Points
V
LVDS
nQx
CMR
GND
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx PART 1 Qx nQy PART 2 Qy tsk(pp)
nQx Qx nQy Qy
tsk(o)
PART-TO-PART SKEW
QxA, nQxA QxA, nQxA QxB, nQxB QxB, nQxB
OUTPUT SKEW
80%
80%
VO D
20% Clock Outputs
t
R
20%
t
F
tsk(b)
BANK SKEW
nQxA, nQxB QxA, QxB
Pulse Width t
PERIOD
OUTPUT RISE/FALL TIME
nCLKx CLKx nQxA, nQxB
odc =
t PW t PERIOD
QxA, QxB
tPD
odc & tPERIOD
ICS8547AY
PROPAGATION DELAY
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REV. A FEBRUARY 4, 2003
Integrated Circuit Systems, Inc.
ICS8547
HEX, LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS CLOCK BUFFERS
VDD out
VDD out
DC Input
LVDS
100
VOD/ VOD out
DC Input
LVDS
out
VOS/ VOS
VOD / DVOD SETUP
VOS / DVOS SETUP
VDD
VDD
out IOS
out
DC Input
LVDS
IOSB out
DC Input
LVDS
out
IOSD
IOS SETUP
IOSD SETUP
LVDS
IOFF VDD
IOFF SETUP
ICS8547AY
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REV. A FEBRUARY 4, 2003
Integrated Circuit Systems, Inc.
ICS8547
HEX, LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS CLOCK BUFFERS APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K CLK_IN + V_REF C1 0.1uF R2 1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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REV. A FEBRUARY 4, 2003
Integrated Circuit Systems, Inc. DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 2 to 5 show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are
ICS8547
HEX, LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS CLOCK BUFFERS
examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 2, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50 HiPerClockS Input
CLK Zo = 50 Ohm nCLK LVPECL R1 50 R2 50 HiPerClockS Input
R3 50
FIGURE 2. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER
BY
FIGURE 3. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input
R5 100 - 200 R6 100 - 200 LVPECL Zo = 50 Ohm
3.3V 3.3V 3.3V C1 R3 125 R4 125 CLK Zo = 50 Ohm C2 nCLK HiPerClockS Input
R4 125
R1 84
R2 84
R5,R6 locate near the driver pin.
FIGURE 4. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
FIGURE 5. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE
BY
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REV. A FEBRUARY 4, 2003
Integrated Circuit Systems, Inc. LVDS DRIVER TERMINATION
Figure 6 shows typical termination for LVDS driver in characteristic impedance of 100 differential (50 single) transmission
ICS8547
HEX, LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS CLOCK BUFFERS
line environment. For buffer with multiple LDVS driver, it is recommended to terminate the unused outputs.
3.3V
3.3V LVDS_Driver
Zo = 50
+ R1 100 Zo = 50
-
FIGURE 6. TYPICAL LVDS DRIVER TERMINATION
RELIABILITY INFORMATION
TABLE 6. JAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8547 is: 1117
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REV. A FEBRUARY 4, 2003
Integrated Circuit Systems, Inc.
ICS8547
HEX, LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS CLOCK BUFFERS
PACKAGE OUTLINE - Y SUFFIX
TABLE 6. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L q ccc 0.45 0 --0.05 1.35 0.17 0.09 BBC MINIMUM NOMINAL 48 --1.40 0.22 -9.00 BASIC 7.00 BASIC 5.50 Ref. 9.00 BASIC 7.00 BASIC 5.50 Ref. 0.50 BASIC 0.60 --0.75 7 0.08 1.60 0.15 1.45 0.27 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
ICS8547AY
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REV. A FEBRUARY 4, 2003
Integrated Circuit Systems, Inc.
ICS8547
HEX, LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS CLOCK BUFFERS
Marking ICS8547AY ICS8547AY Package 48 Lead LQFP 48 Lead LQFP on Tape and Reel Count 250 per tray 1000 Temperature 0C to 85C 0C to 85C
TABLE 7. ORDERING INFORMATION
Part/Order Number ICS8547AY ICS8547AYT
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. ICS8547AY
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REV. A FEBRUARY 4, 2003

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